PDF资料描述
0 0 0 0 FS4 FS3 FS2 FS1 FZC28RF AMP & SERVO SIGNAL PROCESSOR S1L9223B02Figure 17 Waveform at Pin 3 When FS1 Is Switched from 0 to 1, LIST/73When the TIC bus is seized by the MX97102, the BAC-bit on IDP1 is “ 0 ” until the access request is withdrawnAfter a successful bus access, the MX97102 is auto-matically set into lower priority class, that is, a new bus, LIST/73ers, in AB class, with 4 DMOSs, with Rdson of05 (Sink+Source) maximum, in a H-bridge con-figuration Drive voltage for the upper DMOSFETs is provided by a charge pump circuit to en-, LIST/73The information provided in this Materials Disclosure is, to our knowledge, correctHowever, there is no guarantee to completeness or accuracy, as some information is derived from data sources outside the companyAlso, there may not be information included in this statement regarding the minute amounts of dopant and metal materials contained within the electrically active or passive devices contained within the finished product , LIST/73trademarks of PMC-Sierra, IncPROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC, AND FOR ITS CUSTOMERS’ INTERNAL USE PM4354 COMET-QUAD Provides diagnostic, line and per-DS0 , LIST/73tON, tOFF (50% CTL to 90/10% RF) 4 ns TypTransients (In-Band) 10 mV TypInput Power for 1 dB CompressionControl Voltages (Vdc) 0/-5 0/-8, LIST/73These devices can be used as two 8-bit transceivers or one 16-bit transceiver The devices allow datatransmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at thedirection-control (DIR) input The output-enable (OE) input can be used to disable the device so that the busesare effectively isolated, LIST/73C0083C0119C0105C0116C0099C0104C0105C0110C0103 C0068C0105C0111C0100C0101MAXIMUM RATINGSRating Symbol Value UnitReverse Voltage V, LIST/73MULTIPLE OUTPUT MODEL SELECTION CHART – 240W WITH 300 LFM FORCED AIR COOLINGMODELOUTPUT ADJUSTMENT OUTPUT LINE LOAD RIPPLE & NOISE INITIAL SETTINGVOLTAGE RANGE CURRENT (NOTE 1) REGULATION REGULATION %Pk-Pk (NOTE 2) ACCURACY, LIST/73nology to achieve ultra high speed with high output drivewhile maintaining low static power dissipation over a verybroad VCC, LIST/73